The present inventions are related to systems and methods for storing information, and more particularly to systems and methods for reducing loop recovery latency in a storage device.
A typical data processing system receives an analog input signal that is amplified using a variable gain amplifier. The amplified signal is converted to a digital signal and processed using one of a variety of digital processing techniques. Feedback from the digital processing is provided back to a summation element to adjust the low frequency offset. As bit periods have decreased, faster and faster data processing has been developed. Because of this, the feedback latency has grown in terms of the number of bit periods. This latency negatively effects loop stability.
Turning to FIG. 1, a data detection system 100 including a prior art low frequency offset feedback loop is shown. Data detection system 100 includes a variable gain amplifier 110 that receives an analog input signal 105, and provides an amplified output 112. Amplified output 112 is provided to a summation element 199 that sums an analog feedback signal 197 with amplified output 112 to provide a sum output 115. Analog feedback signal 197 is a low frequency offset correction that is more fully described below, and sum output 115 is amplified output 112 less the low frequency offset. Sum output 115 is provided to a magneto-resistive asymmetry correction circuit 120 that yields a corrected output 125. Corrected output 125 is filtered using a continuous time filter 130, and a resulting filtered output 135 is provided to an analog to digital converter 140. Analog to digital converter 140 provides a series of digital samples 145 corresponding to filtered output 135. The series of digital samples 145 are provided to a digital filter 150 that provides a digitally filtered output 155. A data detection algorithm is applied by a data detector 160 to digitally filtered output 155 to recover a Yideal output 165.
Yideal output 165 is provided to a partial response target filter 180 that conforms Yideal to a partial response target and provides a target output 185. Digitally filtered output 155 is provided to a delay circuit 170 that provides a delayed signal 175 that corresponds to digitally filtered output 155 delayed in time sufficient to align it with target output 185. A summation element 192 subtracts target output 185 from delayed signal 175, and provides the result as an error signal 189. Error signal 189 is stored to an offset update register 190. The output of offset update register 190 is converted to analog feedback signal 197 using a digital to analog converter 195. As previously discussed, analog feedback signal 197 is provided to summation element 199 where it is subtracted from amplified output 112.
There can be a substantial latency between the time that summation element 199 provides sum output 115 and when analog feedback signal 197 corresponding to sum output 115 is available. As this latency grows to several bit periods, it can result in substantial loop instability as analog feedback signal 197 can be applied well after the condition it was intended to correct has resolved itself. Indeed, in some cases, analog feedback signal 197, rather than operating as a negative feedback may operate as a positive feedback accentuate an undesired operational condition.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for reduced latency data processing.